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Ch1 指令集架構（ISA）
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22. ISA、RISC vs CISC、Endianness、Open ISA
#CC-01-022
中
ISA
RISC vs CISC
Endianness
Open ISA
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For instruction set architecture (ISA), which of the following statements are true?
A
(a) RISC CPUs usually use fixed and simple instruction formats, which may offer better execution efficiency for pipelining than CISC CPUs.
B
(b) The choice of Big/Little endian determines the memory ordering and is nothing to do with the ISA design.
C
(c) The purpose of Open ISA is to allow "open source" of CPU RTL codes.
D
(d) An ISA keeping the source (rs1 and rs2) and destination (rd) registers at the same position in all formats can simplify decoding (such as RISC-V), whereas MIPS has overlapped fields for rs2 and rd, which needs multiplexors.
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完整推導請見《WH 資工筆記 · 計算機組織與結構》Ch1 指令集架構（ISA）
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