Given a pipelined processor that includes a directed-mapped data cache where the length of memory address is 32 bits. The size of tag, index, and offset fields in such a directed-mapped data cache are 26 bits, 4 bits, and 2 bits for each. This processor executes the program 1 and observes its cache miss rate is high. What kind of cache misses causes such a problem when using a directed-mapped cache in this processor?

        addi  $t0   $0    3
loop:   beq   $t0   $0    done
        lw    $t1   0x4($0)
        lw    $t2   0x8($0)
        lw    $t3   0xC($0)
        lw    $t4   0x10($0)
        addi  $t0   $t0   -1
        j     loop
done:

（Program 1）