Suppose that a cache memory's (L1) access time is "C ns" and a main memory's (L2) access time is "M ns". In this architecture, 60% of the memory accesses are read and remaining all are writing requests. If the hit ratio of read operation can achieves "H" and that of writing operation is 1, what is the average memory access time (AMAT) when a write-through protocol is adopted on the cache?