(2%) In a system with a non-coherent CPU data cache, a device performs DMA writes into a memory buffer that the CPU later reads. Which action is correct for the CPU/driver to ensure it reads the newly DMA-written data?
A Before starting the DMA write, the CPU must invalidate the cache lines of the destination buffer; after DMA completion, no cache maintenance is needed because DMA writes update memory directly.
B The CPU should clean (write back) the cache lines after DMA completion, because writing back ensures the cache and memory match the device output.
C No cache maintenance is required as long as the buffer is aligned to cache-line boundaries and the DMA length is a multiple of the cache-line size.
D After DMA completion, the CPU must invalidate (or otherwise ensure invalidation of) the cache lines covering the buffer before reading it, because the CPU cache may still hold stale copies.
