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Ch6 記憶體（Memory）
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79. Cache Associativity、Branch Offset、Pipeline Register
#CC-06-079
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Cache Associativity
Branch Offset
Pipeline Register
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Which of the following statements are true?
A
Increasing associativity of a cache would usually reduce the miss rate and the hit time.
B
The branch offset field in the MIPS instruction is specified as a multiple of 4, i.e. a branch offset of 1 means 4 bytes. This enables a much larger range of branch offsets than if the offset were specified in bytes.
C
We can always increase the hit rate by increasing the size of a cache.
D
Pipeline registers between stages are necessary when performing pipelining.
E
MIPS instructions are 32 bits.
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