Consider a 16-bit computer with a hierarchical memory system consisting of a disk, a $2^{16}$-byte main memory using byte-addressing, and a two-level cache with primary cache of $2^9$-byte data inside CPU. The primary cache is designed as follows. It is a direct mapped cache. Each block is 16-word long and the replacement policy is LRU. The OS adopts a 16-bit virtual address with a page size of 0.5KB.