You have designed a brand new CPU: NYCU (New Younker Compute Unit). We know:

$real\ CPI = ideal\ CPI + data\ access\ prob * avg\ stall\ cycles$ $avg\ stall = miss\ rate * miss\ penalty$

Assume that NYCU can run at 2GHz and its lw/sw share 25% of total $N$ instructions. Let us ignore the instruction cache issue and ideal CPI is 1. The access time of main memory is 100 ns.