作業系統›Ch7 記憶體管理第 18 題／共 40 題
18. Segmented Paging、Segment Base Address
#OS-07-018易Segmented PagingSegment Base Address
題組題幹（本題：第22題，共 5 小題）點擊展開
Consider a byte-addressable computer system with a 13-bit logical address, a total physical memory size of 4 KiB, and a page size of 64 Bytes. The system uses a segmented paging architecture where the logical address is divided into a Segment Number and a Segment Offset. The segment table provides a Base Address which is added to the Segment Offset to form a linear Address. This Linear Address is then translated via a single-level Page Table to a Physical Address.
Segment Table (Segment Base Addr, Binary):
| Idx | Segment Base Addr |
|---|---|
| 0 | 0000,0000,0000 |
| 1 | 0010,0000,0000 |
| 2 | 0001,1000,0000 |
| 3 | 0011,0000,0000 |
| 4 | 0000,1000,0000 |
| 5 | 0100,0000,0000 |
| 6 | 0101,0000,0000 |
| 7 | 0110,0000,0000 |
Page Table (Frame Number, Decimal)：
| Idx | Frame Number |
|---|---|
| 24 | 12 |
| 25 | 5 |
| 26 | 33 |
| 27 | 8 |
What is the Segment Base Address (in hexadecimal) retrieved from the Segment Table?
📄 交大115
▤完整推導請見《WH 資工筆記 · 作業系統》Ch7 記憶體管理