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計算機組織與結構
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Ch2 計算機算術（Arithmetic）
第 13 題／共 26 題
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CC 13/26
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13. Multiplier Design、Carry Look-Ahead Adder
#CC-02-013
中
Multiplier Design
Carry Look-Ahead Adder
📝
☆
Which of the following statements are correct?
A
(a) Fig. 2 shows a correct 3-bit×3-bit multiplier.
B
(b) Fig. 3 shows a wrong 32-bit×32-bit multiplier.
C
(c) The most significant bit of a carry look-ahead adder often experiences elevated input loading, leading to increased delays. Employing a multi-level carry look-ahead adder helps mitigate the issue of high input loading.
D
(d) Consider the 16-bit two-level carry look-ahead adder in Fig. 4 and the timing of transitioning to correct value on each signal line,
c
1
c_1
c
1
transitions to correct signal before
c
4
c_4
c
4
to
c
15
c_{15}
c
15
,
G
(
4
i
−
4
)
−
(
4
i
−
1
)
G_{(4i-4)-(4i-1)}
G
(
4
i
−
4
)
−
(
4
i
−
1
)
and
P
(
4
i
−
4
)
−
(
4
i
−
1
)
P_{(4i-4)-(4i-1)}
P
(
4
i
−
4
)
−
(
4
i
−
1
)
transition to correct values prior to
c
4
i
c_{4i}
c
4
i
, for
i
=
1
i = 1
i
=
1
to 3, and
c
4
i
c_{4i}
c
4
i
transitions to correct value prior to
c
4
i
+
1
c_{4i+1}
c
4
i
+
1
to
c
4
i
+
3
c_{4i+3}
c
4
i
+
3
, for
i
=
1
i = 1
i
=
1
to 3.
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