Consider the above ALU design. The control signals are grouped as (Ainvert, Binvert, Operation[1], Operation[0]). Which of the following statements are true?
$t1+$t2
addu $t0, $t1, $t2; nor $t3, $t1, $zero; sltu $t3, $t3, $t2; beq $t3, $zero, Overflow
