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Ch5 管線化（Pipeline）
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56. Dynamic Scheduling、ISA Design、RISC
#CC-05-056
中
Dynamic Scheduling
ISA Design
RISC
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Which of the following statements are NOT true for instruction set design and CPU implementation?
A
The advantages of dynamic scheduling include memory latency hiding and resolving real dependence which is unknown at compile time.
B
For single-cycle implementation of CPU, the clock cycle is determined by the longest possible path.
C
Compared to Memory-Memory architecture or Register-Memory architecture, Register-Register architecture has the advantage of having larger variation in Clock Cycle Per Instruction (CPI).
D
Reduced Instruction Set Computer (RISC) has become mainstream products.
E
Single-cycle implementation of CPU is more suitable for pipeline implementation compared with multi-cycle implementation.
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完整推導請見《WH 資工筆記 · 計算機組織與結構》Ch5 管線化（Pipeline）
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