A processor runs at 4 GHz and has a CPI of 1.4 without including the stall cycles due to cache misses. Load and store instructions count 30% of all instructions. The processor has an I-cache and a D-cache. The hit time is 1 clock cycle. The I-cache has a 3% miss rate. The D-cache has a 5% miss rate on load and store instructions. The miss penalty is 50 ns, which is the time to access and transfer a cache block between main memory and the cache. Which following statement are correct?