Given a processor with two caches: an I-cache and a D-cache, and the miss penalty is 200 cycles for all misses. Assume the I-cache miss rate is 2%, D-cache miss rate is 4%, and the percentage of all lw and sw instructions is 50%. If the processor has a CPI of 2 without any memory stalls. Which of following statements are true when memory stall is considered? (Note, each statement is independent.)