計算機組織與結構›Ch6 記憶體（Memory）第 25 題／共 83 題
25. Set-Associative Cache、Tag Bits
#CC-06-025易Set-Associative CacheTag Bits
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A pipelined processor contains 64 KB L1 data cache, where the length of memory address is 32 bits, the block size is 64 bytes. This data cache employs 4-way set associative cache architecture. The size of physical memory on this processor is 4 GB.
How many bits are used in tag of such a data cache?
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▤完整推導請見《WH 資工筆記 · 計算機組織與結構》Ch6 記憶體（Memory）