Consider the execution of the following code on the 5-stage pipelined processor. The processor has both the hazard detection unit and the forwarding unit for data hazard. Assume that the following code sequence executes starting from clock cycle 1. At clock cycle 8, where do the two ALU inputs come from?

add x28, x31, x29
ld  x31, 32(x29)
and x30, x29, x31
sd  x5, 20(x30)
sub x5, x5, x30
or  x29, x29, x30