計算機組織與結構›Ch5 管線化(Pipeline)第 20 題/共 58 題
20. Pipeline、Control Signals
#CC-05-020中PipelineControl Signals
題組題幹(本題:第34題,共 4 小題)點擊展開
Consider the execution of the following code on a 5-stage pipelined processor, shown in the Figure below. Note that the processor includes both a hazard detection unit and a forwarding unit for data hazard, though these components are not shown in the figure. Assume the code sequence starts execution at clock cycle 1. Please answer the following questions.
ld x31, 32(x5)
sub x30, x31, x5
ld x31, 20(x30)
add x29, x29, x30
or x5, x5, x30
What are the values of signals ALUsrc and MemToReg, respectively, at clock cycle 5?

📄 交大114
▤完整推導請見《WH 資工筆記 · 計算機組織與結構》Ch5 管線化(Pipeline)