The following statements describe three pairs of pipelined processors. In each pair, the processors are identical except for the specified feature. In all cases, the processors execute the same compiled program. Ignore differences in execution time, pipeline stalls, and throughput. Consider only whether the processors may produce different architectural results.

In Case A, processor A resolves data hazards using interlocks, while processor B uses full bypassing.

In Case B, Processor A handles control hazards by stalling the pipeline until the branch target is known. Processor B uses a 'predict-not-taken' scheme and flushes the pipeline if the branch is taken.

In Case C, processor A has a single memory port shared between instruction fetch and data access, while processor B has no structural hazards.