計算機組織與結構›Ch5 管線化(Pipeline)
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25. Pipeline、Data Hazard、Branch Resolution、CPI
#CC-05-025難PipelineData HazardBranch ResolutionCPI

Assume that we have a 5-stage processor that has neither data forwarding nor branch prediction. It has separate instruction and data memory. Bubbles will be inserted when there are hazards. The processor always resolves the branch target at stage 2 (the decode stage). Which of the following statements are true when the following code segment is executed?

      addi $t1, zero, zero
loop: addi $t1, $t1, 1
      lw   $s0, 2000($t1)
      subi $t2, $s0, 2
      sw   $t2, 4000($t1)
      bne  $t1, $t3, loop
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