For a MIPS 5-stage pipelined CPU with data forwarding and stall mechanisms been implemented, which of following statements are true for the code sequence below? You may refer to the following code sequence and the CPU pipeline figure (same datapath figure as the previous question).

add $s2, $s2, $s3
lw  $s1, 0($s2)
addi $t1, $s2, 8
sw  $t2, 0($s1)
lw  $t3, 0($s1)
add $s3, $t3, $s2
sub $s3, $s3, $s2