計算機組織與結構›Ch5 管線化（Pipeline）第 23 題／共 58 題
23. Single-Cycle CPU、Pipeline、CPI、Critical Path
#CC-05-023中Single-Cycle CPUPipelineCPICritical Path
Two CPUs are implemented to execute exactly the same ISA. Assume that CPU A is a single-cycle implementation while CPU B is a five-stage pipelined implementation. The instruction and data memory devices are zero wait state memory for both CPU. Which of the following statements are true when both CPUs runs the same program C with finite execution time?
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