Assume that we have a classical five-stage pipelined 32-bit MIPS processor with a branch predictor and all required forwarding mechanisms. Which of the following statements are true?
A (a) If a load instruction is immediately followed by a conditional branch that is on the load result, and assume that the branch condition is evaluated on the decode stage. One stall cycle is needed to execute the two instructions properly.
B (b) If the 16-bit immediate value in a branch instruction is imm , the branch target address, is computed by PC = PC + 4 + sign-ext(imm ). Note that sign-ext(imm ) means sign extension of the parameter imm to 32-bit.
C (c) For better performance, the branch target buffer that stores the destination PC for a branch is usually implemented as a tagged memory.
D (d) A branch predictor using the information of both a local branch instruction and the global behavior of recently executed branches is called a correlating predictor.
