The following in-order pipelined five-stage MIPS processor design shown in Fig. 1 has a bug:

Note that the processor has no forwarding paths, and if it detects data hazards at the decode stage (the hazard control unit is not shown), the pipeline stages will stall properly. If we use the buggy processor to execute the following code segment:

add $4, $1, $2
or  $0, $1, $1
addi $2, $2, 3
add $3, $4, $3
add $1, $4, $0

and assume that initially the registers $0~$4 contains the values 0~4, respectively. That is, register $0 is 0, register $1 is 1, …, etc. Which of the following statements are true right after the writeback stage of the fourth instruction (add $3, $4, $3) is complete?