Consider the execution of the following code on a 5-stage pipelined processor, shown in the Figure below. Note that the processor includes both a hazard detection unit and a forwarding unit for data hazard, though these components are not shown in the figure. Assume the code sequence starts execution at clock cycle 1. Please answer the following questions.

ld  x31, 32(x5)
sub x30, x31, x5
ld  x31, 20(x30)
add x29, x29, x30
or  x5, x5, x30